1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a step-up potential supply circuit for use in a semiconductor storage device such as a dynamic random access memory.
2. Description of the Background Art
FIG. 13 is a block diagram showing the overall circuit structure of a conventional DRAM. As shown in this diagram, an address signal inputted from an external address pin P1 passes the address buffer 21 and is time-divided; the row address is inputted to the row decoder 22 and the column address to the column decoder 23. The row decoder 22 decodes the row address, according to which result the word driver 24 selectively activates a word line WL in the memory cell array 25. The memory array 25 includes DRAM memory cells arranged in a matrix, where each row is connected to a common word line WL and each column is connected to a common bit line BL.
The column decoder 23 decodes the column address, according to which result a bit line, or a column selecting line, is selected. Then, when reading, data in the memory cell connected to both of the selected word line and bit line is amplified in the sense amplifier 26 and then outputted from the output pin P0 through a preamplifier (not shown) and the output buffer 27.
FIG. 14 shows the structure of a memory cell of the DRAM in detail. A memory cell of the DRAM is formed of one NMOS transistor 215 and one capacitor 217. The NMOS transistor 215 has its gate connected to the word line WL, one of its source/drain connected to the bit line BL and the other connected to one electrode of the capacitor 217. The substrate potential of the semiconductor substrate in which this NMOS transistor 215 is formed is (when a p-type substrate is used) usually at a negative, back gate potential (Vbb). The other electrode of the capacitor is set at a cell-plate potential Vcp.
The operation of writing "H" data (a Vcc level) into the memory cell is explained referring to FIG. 15. A Vcc level is transferred to the bit line BL by the sense amplifier 26 (refer to FIG. 13). Then, the word line WL is caused to rise to write Vcc into the storage node SN of the capacitor.
FIG. 16 shows the conditions of the voltage applied to the NMOS transistor at this time. When the bit line BL (source) attains the Vcc level, a large back gate potential Vbs (Vbb-Vcc) is applied to it due to the substrate potential Vbb. Originally, the NMOS transistor 215 of the memory cell has a higher threshold (Vth) than usual peripheral NMOS transistors to reduce the sub-threshold leakage current and to improve the refresh characteristics.
Then, when the source potential on the bit line BL rises to the Vcc level and the back gate voltage Vbs increases, the threshold of the NMOS transistor 215 of the memory cell further increases. FIG. 17 is a graph showing the increase of the threshold of the transistor of the memory cell due to the substrate effect. As shown in this diagram, while the threshold of the NMOS transistor 215 is Vt1 with Vbs=Vbb, it becomes as high as Vt2 when the Vcc level is written into the capacitor 217.
The "H" level of the word line WL must strongly turn on the NMOS transistor 215 to certainly transfer the Vcc level to the memory cell. The "H" level of the word line therefore requires the level of Vcc+Vth plus operation margin .alpha.; (Vcc+Vth+.alpha.).
FIG. 18 shows the relation between the word line WL and the power-supply potential Vcc. Since the threshold of the memory cell does not fall in proportion to the Vcc level, that is, since it takes almost the same value, the potential on the word line WL is proportional to Vcc. Nowadays, a power-supply for the step-up potential Vpp is usually used to set the potential on the word line WL. FIG. 19 and FIG. 20 show examples of circuit structure of a word driver.
In FIG. 19, the NAND gate 33 receives the row address and outputs the decoded result (select with "L" and unselect with "H") to the word driver 24. The word driver 24 is formed of PMOS transistors 34 and 35 and an NMOS transistor 36. The sources of the PMOS transistors 34 and 35 receive the step-up potential Vpp, and the PMOS transistor 35 and the NMOS transistor 36 form a CMOS inverter. The output portion of this CMOS inverter is connected to the word line WL and to the gate of the PMOS transistor 34. The input portion of the CMOS inverter and the drain of the PMOS transistor 34 receive the output of the NAND gate 33.
With this structure, when the output of the NAND gate 33 is "L", the PMOS transistor 35 turns on and the NMOS transistor 36 turns off, and therefore the word line WL is provided with the step-up potential Vpp. On the other hand, when the output of the NAND gate 33 is "H", the PMOS transistor 35 turns off and the NMOS transistor 36 turns on, and then the word line WL is set at an "L" level (the ground level). Furthermore, the PMOS transistor 34 turns on and the step-up potential Vpp is applied to the input portion of the CMOS inverter, and then the PMOS transistor 35 certainly turns off.
In FIG. 20, the inverter 37 receives the output from the NAND gate 33 and the output of the inverter 37 (the "H" level is the step-up potential Vpp) is applied to the gate of the NMOS transistor 39 through the NMOS transistor 38. The NMOS transistors 39 and 40 are connected in series between the signal RX and the ground level, the signal RX supplying the step-up potential Vpp.
With this structure, when the output of the NAND gate 33 is "L", the output of the inverter 37 is "H" (the step-up potential Vpp), and then the NMOS transistor 39 turns on and the NMOS transistor 40 turns off. Then, the word line WL is provided with the step-up potential Vpp. On the other hand, when the NAND gate 33 is "H", the NMOS transistor 39 turns off and the NMOS transistor 40 turns on, and then the word line WL is set at the "L" level (the ground level).
FIG. 21 is a circuit diagram showing the basic principle of a conventional Vpp generating circuit. The precharge circuit 41 (shown as a power-supply and a diode in FIG. 21) precharges the node NA to the Vcc level. The pump capacitor 42 is connected to the node NA, one electrode of which is thus charged. After the precharging, the oscillator 44 applies an oscillation signal (amplitude of GND and Vcc) to the other electrode of the capacitor 42. Then, the node NA is stepped up from the Vcc level to the doubled Vcc level, which potential is transferred to the step-up potential node Npp. FIG. 21 shows the diode 43 as a switch element for passing the potential to the step-up potential node Npp.
FIG. 22 shows an example of a charge pump circuit. A pulse-like clock signal CLK is inputted. The signal CLK is applied to one electrode of the capacitor 65 and one electrode of the capacitor 66. The node NA on the other electrode side of the capacitor 67 is connected to the drain of the NMOS transistor 73 and the node NB on the other electrode side of the capacitor 65 is connected to the gate of the NMOS transistor 73. The NMOS transistor 69, having common drain and gate, is interposed between the power-supply potential Vcc and the node NA, and the NMOS transistor 71, having common drain and gate, is interposed between the power-supply potential Vcc and the node NB.
With this structure, before starting operation, the nodes NA and NB are precharged by the NMOS transistors 69 and 71 to the power-supply potential Vcc, or to a potential at a level lower than the power-supply potential Vcc by the threshold voltage. When starting operation, the clock signal CLK is inputted to the capacitors 65 and 67. Then, as the clock signal CLK rises from the ground level (0V) to the power-supply potential Vcc, the potentials at the nodes NA and NB rise from the power-supply potential Vcc level to the doubled, 2Vcc level because of the capacitive coupling of the capacitors 67 and 65. The potential at the 2Vcc level at the node NA is supplied to the step-up potential node Npp as the step-up potential Vpp through the NMOS transistor 73. However, supplied to the step-up potential node Npp is a potential lower than 2Vcc by the threshold voltage of the NMOS transistor 73, because the last driver of the charge pump circuit is the NMOS transistor 73.
Next, FIG. 23 shows a circuit using a triple-well structure. As shown in FIG. 23, a pulse-like clock signal CLK is inputted. The signal CLK is applied to one electrode of the capacitor 45 and to one electrode of the capacitor 46. The node NA on the other electrode side of the capacitor 45 is connected to the drain of the NMOS transistor 47 and the node NB on the other electrode side of the capacitor 46 is connected to the gate of the NMOS transistor 47.
As shown in the section in FIG. 24, since the drain of the NMOS transistor 47 is electrically connected to the P-well region 231, the island in which the NMOS transistor 47 is formed, a potential is transferred by the PN junction from the P-well region 231 to the N.sup.+ region 232, or the source of the NMOS transistor 47.
While it is hence possible to cause the step-up potential Vpp to be outputted from the step-up potential node Npp with operation similar to that of the charge pump circuit shown in FIG. 22, the step-up potential Vpp is lower than the doubled Vcc level by the PN junction voltage Vv. However, as the PN junction voltage Vv is lower than the threshold of the NMOS transistor, the charge pump circuit shown in FIG. 23 can generate the step-up potential Vpp at a higher level than the charge pump circuit shown in FIG. 22.
FIG. 25 is a circuit diagram showing an example of a charge pump circuit in detail. As shown in this diagram, the charge pump circuit is formed of capacitors 75 and 77, a level converting circuit 79, and an NMOS transistor 81.
The capacitor 75 is interposed between the node to which the clock signal CLK is inputted and the node NA. The level converting circuit 79 enlarges the amplitude of the clock signal CLK and outputs it to the capacitor 77. The capacitor 77 is interposed between the level converting circuit 79 and the node NB. The NMOS transistor 81 is interposed between the node NA and the step-up potential node Npp, the gate of the NMOS transistor 81 serving as the node NB.
This structure, that is, providing the gate of the NMOS transistor 81 with a potential level higher than the potential level (2Vcc level) inputted to the gate of the NMOS transistor 73 of FIG. 22 prevents the potential supplied from the node NA to the step-up potential node Npp from being lowered from 2Vcc by the threshold voltage of the NMOS transistor 81.
FIG. 26 is a circuit diagram showing the level converting circuit 79 of FIG. 25 in detail. The same parts as those in FIG. 25 are shown at the same reference characters and not fully described again.
Referring to FIG. 26, the level converting circuit 79 is formed of NMOS transistors 83, 85, PMOS transistors 87, 89 and an inverter 91. The PMOS transistor 87 and the NMOS transistor 83 are connected in series between the step-up potential Vpp and the ground level. The PMOS transistor 89 and the NMOS transistor 85 are connected in series between the step-up potential Vpp and the ground level. The clock signal CLK as an input signal IN is applied to the gate of the NMOS transistor 83. The clock signal CLK is inverted by the inverter 91 and inputted to the gate of the NMOS transistor 85. The PMOS transistor 89 has its gate connected to the drain of the NMOS transistor 83 and the PMOS transistor 87 has its gate connected to the drain of the NMOS transistor 85. An output signal OUT is outputted from the drain of the NMOS transistor 85 to the capacitor 77 of FIG. 25.
Referring to FIG. 25 and FIG. 26, operation of the charge pump circuit will be explained. When the clock signal CLK at the ground level is inputted to the level converting circuit 79, the level converting circuit 79 outputs the signal OUT on the ground level to the capacitor 77. Next, when the clock signal CLK goes from the ground potential GND level to the power-supply potential Vcc, the level converting circuit 79 outputs the signal OUT at the step-up potential Vpp level to the capacitor 77. That is to say, the capacitor 77 is provided with the step-up potential Vpp, and then the potential at the node NB becomes higher than 2Vcc because of the capacitive coupling. This allows the potential at the 2Vcc level at the node NA to be transferred to the step-up potential node Npp as the step-up potential Vpp without affected by the threshold voltage of the NMOS transistor 81. That is to say, the potential transferred to the step-up potential node Npp is not lowered from 2Vcc by the threshold voltage of the NMOS transistor 81.
FIG. 27 is a circuit diagram showing another example of a charge pump circuit in detail. Referring to FIG. 27, the charge pump circuit is formed of an inverter 93, diodes 95 and 97, NMOS transistors 99, 101, a PMOS transistor 103 and capacitors 105, 107 and 109.
The capacitor 107 is connected between the node to which the clock signal CLK is inputted and the node NC. The NMOS transistor 101 is connected between the node NC and the step-up potential node Npp, whose gate is connected to the node NB. The input node of the inverter 93 is connected to the input node for the clock signal CLK and its output node is connected to the gate of the PMOS transistor 103 and the gate of the NMOS transistor 99. The diode 95, the PMOS transistor 103 and the NMOS transistor 99 are connected in series between the power-supply potential Vcc and the ground level. The capacitor 105 is interposed between the input node for the clock signal CLK and the node NA. The capacitor 109 is interposed between the drain of the NMOS transistor 99 and the node NB. The diode 97 is interposed between the power-supply potential Vcc and the node NB.
FIG. 28 is a timing diagram for describing operation of the charge pump circuit of FIG. 27. Referring to FIG. 27 and FIG. 28, the operation of the charge pump circuit will be explained. The node NA is charged to the power-supply potential Vcc by the diode 95 as a precharge circuit. When the clock signal CLK goes from 0V to the power-supply potential Vcc, the capacitive coupling causes the potential at the node NA to become the 2Vcc level twice as large as the power-supply potential Vcc. On the other hand, a potential of 0V is applied to the gate of the PMOS transistor 103 and it turns on. Accordingly, the potential at the 2Vcc level is provided to the capacitor 109 from the node NA. The operation explained so far corresponds to the operation of enlarging the amplitude of the clock signal CLK from between the ground level (0V) and the power-supply potential Vcc to between the ground level (0V) and 2Vcc. Since the capacitor 109 is thus provided with a potential at the 2Vcc level, the potential at the node NB is stepped up from the power-supply potential Vcc level to the triple, 3Vcc level. Accordingly, the potential at the 2Vcc level at the node NC produced by the capacitor 107 is intactly transferred to the step-up potential node Npp by the NMOS transistor 101 receiving the 3Vcc potential at its gate without being decreased the threshold voltage of the NMOS transistor 101.
FIG. 29 shows an example of utilization of the Vpp power-supply. The step-up potential Vpp produced by the charge pump circuit explained above is used as an operation power-supply for circuits requiring the step-up potential Vpp, such as the word driver 24, the RX driver 18, etc. When the DRAM enters a running state, the step-up potential Vpp generated from the charge pump circuit is consumed and its potential decreases. When the step-up potential Vpp remains decreased, the potential on a word line WL in an active state will not rise sufficiently, or it will take long before attaining a desired potential, leading to deterioration of performance or malfunction of the DRAM.
If the charge pump circuit is always kept operating to maintain the step-up potential Vpp at a desired level, however, the power consumption increases. Then, the circuit shown in FIG. 30 is suggested. As shown in FIG. 30, a detecting circuit 19 is provided to detect whether the step-up potential Vpp is maintaining a certain level. When the step-up potential Vpp falls below the certain level, it provides a pump active signal OE at "L" to cause the ring oscillator 20 to operate. Then the charge pump circuit 28 generates the step-up potential Vpp at the step-up potential node Npp in response to the clock signal CLK from the ring oscillator 20. On the other hand, when the potential level at the step-up potential node Npp attains or exceeds the certain level, the detecting circuit 19 provides the pump active signal OE at "H" to stop the operation of the ring oscillator 20. The charge pump circuit 28 then stops generating the step-up potential Vpp to the step-up potential node Npp.
FIG. 31 and FIG. 32 are circuit diagrams showing examples of structure of the detecting circuit 19. In FIG. 31, an NMOS transistor 111 and a resistor 115 are connected in series between the step-up potential node Npp and the ground level and the power-supply potential Vcc is applied to the gate of the NMOS transistor 111. The NMOS transistor 111 has a channel length larger than usual to realize a threshold Vth similar to that of the transistor forming a memory cell (the NMOS transistor 215 in FIG. 13). The signal obtained from the node NO between the NMOS transistor 111 and the resistor 115 becomes the pump active signal OE.
Accordingly, in the circuit in FIG. 31, the pump active signal OE goes "H" when the step-up potential Vpp exceeds (Vcc+Vth) and goes "L" when it falls below it.
In FIG. 32, the detecting circuit 19 is formed of PMOS transistors 117, 119 and a resistor 121. The PMOS transistor 117, the PMOS transistor 119 and the resistor 121 are connected in series between the step-up potential node Npp and the ground level. The PMOS transistor 117 is diode-connected and the gate of the PMOS transistor 119 is provided with the power-supply potential Vcc. The threshold voltage of the PMOS transistors 117 and 119 is taken to be Vthp. The signal obtained from the node NO between the drain of the PMOS transistor 119 and the resistor 121 becomes the pump active signal OE.
Hence, in the circuit shown in FIG. 32, the pump active signal OE goes "H" when the step-up potential Vpp exceeds (Vcc+2Vthp) and goes "L" when it falls below it.
Thus, in the detecting circuits 19 having the structures shown in FIG. 31 and FIG. 32, when the charge is consumed from the step-up potential node Npp and the step-up potential Vpp drops, the transistor 111 (119) turns off and the pump active signal OE goes "L" to cause the charge pump circuit to operate to maintain the step-up potential Vpp above a set value.
Consider DRAM operation at a power-supply potential Vcc as low as 2V, or lower. When the step-up potential Vpp is generated by using the charge pump circuit having the structure described above, the capability (the maximum attainable level) of the charge pump circuit can, even if an ideal circuit, attain only the doubled power-supply potential Vcc. That is to say, the step-up potential Vpp has an inclination twice that of a change in the power-supply potential Vcc. However, the threshold (Vth) of the memory cells can not be lowered in proportion to Vcc, since the refresh characteristics must be maintained.
In FIG. 33, the line Ld shows a change of the power-supply potential Vcc. That is to say, the vertical axis in FIG. 33 shows the power-supply potential Vcc for the line Ld. The threshold voltage Vth of the NMOS transistor 215 (FIG. 2) of a memory cell can not be lowered at the same inclination as the power-supply potential Vcc. That is to say, the threshold voltage Vth has almost the same value irrespective of the power-supply potential Vcc. Accordingly, the minimum potential level required for the step-up potential Vpp has approximately the same inclination as the power-supply potential Vcc. The line Lc shows the minimum potential level required for the step-up potential Vpp.
In practice, the minimum potential level required for the step-up potential Vpp further includes, in addition to the value (Vcc+Vth), the operation margin m2 (hundreds of millivolts) and the control margin m1 (hundreds of millivolts) for controlling the detecting circuit 19 (FIG. 30). The line Lb shows the minimum potential level actually required for the step-up potential Vpp. The threshold voltage Vth of the NMOS transistor forming a memory cell can not be lowered at approximately the same inclination as the power-supply potential Vcc because it is necessary to maintain the refresh characteristics and the control margin m1 is required to prevent the charge pump circuit 28 (FIG. 30) from operating too frequently to increase the power consumption. In summary, the actually required minimum potential level for the step-up potential Vpp is (Vcc+Vth+m1+m2; the line Lb in FIG. 33).
The maximum step-up potential Vpp that a step-up potential generating circuit can generate rapidly decreases as the power-supply potential Vcc decreases. The line La in FIG. 33 shows the potential level of the maximum step-up potential Vpp that the step-up potential generating circuit can generate.
This rapid decrease is due to the fact that the maximum step-up potential Vpp that the step-up potential generating circuit can generate has an inclination twice that of the power-supply potential Vcc, since the maximum step-up potential Vpp that the step-up potential generating circuit can generate is at the 2Vcc level.
In FIG. 33, when the power-supply potential Vcc is Vb (about 3.3 V), that is, when the power-supply potential Vcc is relatively large, there is no problem because the maximum step-up potential Vpp (the line La) that the step-up potential generating circuit can generate sufficiently exceeds the actually required step-up potential Vpp (the line Lb).
A problem arises, however, when the power-supply potential Vcc is Va (about 1.5V) or lower, that is, when the power-supply potential Vcc is as small as 2V, or smaller. That is to say, when the power-supply potential Vcc is Va, the maximum step-up potential Vpp (the line La) that the step-up potential generating circuit can generate is almost equal to the actually required minimum step-up potential Vpp (the line Lb). When the power-supply potential Vcc is lower than Va, the maximum step-up potential Vpp that the step-up potential generating circuit can generate becomes smaller than the actually required minimum step-up potential Vpp. Thus there is the problem that the conventional step-up potential generating circuit can not supply the actually required step-up potential Vpp if the power-supply potential Vcc is small.
FIG. 34 is a circuit diagram showing a power-supply for supplying the step-up potential Vpp, which is used to explain another problem of the conventional DRAM. The same parts as those in FIG. 21 are shown at the same reference characters and not fully explained. The switch 49 in FIG. 34 corresponds to the diode 43 in FIG. 21.
Referring to FIG. 34, when the capacitance value of the negative side capacitor 48 is taken as Cv, the capacitor 48 accumulates a charge of (Cv.multidot.Vpp). In this sense, the step-up potential node Npp to which the capacitor 48 is connected can be regarded as a power-supply for supplying the step-up potential Vpp.
In one operating period (in one cycle), the power-supply Npp consumes a certain fixed amount of charge, that is, (Cv.multidot.Vpp). Hence, if the consumed charge is not compensated for in one cycle in the direction of the arrow `a` from the step-up potential generating circuit, the step-up potential Vpp may fall below the certain potential when the next cycle starts, which may lead to a malfunction.
When the capacitor (pump capacitor) 42 has a capacitance of Cp, the amount of charge which can be supplied from the step-up potential generating circuit is Cp.multidot.(2Vcc-Vpp). If the (2Vcc-Vpp) has a small value, that it, if the difference between the maximum step-up potential that the step-up potential generating circuit can generate and the minimum required potential for the step-up potential is small, it is necessary to set a large value for the capacitor (pump capacitor) 42. This causes the problem of an increase in chip size.
Since a charge pump circuit for the step-up potential Vpp having an attainable level of doubled Vcc is not sufficient when operating with a low power-supply potential, use of a pump circuit providing a value larger than the twice will be one of the solutions. Such a pump circuit structure is described in detail in Japanese Patent Laying-Open No. 7-46825. For the object of realizing a DRAM with a wide range of power-supply potential, generating a Vpp larger than the doubled Vcc works with a low power-supply potential Vcc. However, with a high Vcc, in addition to the fact that the level larger than the doubled Vcc is unnecessary, the large capacitance of the pump capacitor in the charge pump circuit will supply excessive charge to excessively raise the step-up potential Vpp, bringing about new problems like deterioration of reliability and increase in the power consumption.